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TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 1.5a multiple led camera flash and video light driver with i 2 c tm compatible interface check for samples: TPS61310 , tps61311 1 features description the tps6131x family is an integrated solution with a 23 ? operational modes: wide feature set for driving up to three leds for still- ? video light and flash strobe camera flash strobe and video-camera lighting ? voltage regulated converter: 3.8v...5.7v applications. it is based on a high efficiency with down mode synchronous boost topology with combinable current sinks to drive up to three white leds in parallel. the ? standby: 2 a (typ.) 2mhz switching frequency allows the use of small ? led v f measurement and low-profile 2.2 h inductors. to optimize overall ? power-save mode for improved efficiency at efficiency, the device operates with a low led- low output power, up to 95% efficiency feedback voltage and regulated output-voltage adaptation. ? i 2 c compatible interface up to 3.4mbits/s the device integrates a control scheme that ? dual wire camera module interface automatically optimizes the led current flash budget ? zero latency tx-masking input as a function of the battery voltage condition. ? hardware reset input the tps6131x not only operates as a regulated ? privacy indicator led output current source, but also as a standard voltage boost ? gpio/power good output regulator. the device enters power-save mode operation at light load currents to maintain high ? various safe operation and robust handling efficiency over the entire load current range. these features: operating modes can be useful to supply other high ? led temperature monitoring power devices in the system (e.g. hands-free audio ? open/short led detection/protection pa). ? integrated led safety timer to simplify video light and flash synchronization with ? automatic battery voltage droop the camera module, the device offers a dedicated monitoring and protection control interface (strb0, strb1) for zero latency led turn-on time. ? smooth led current ramp-up/down ? undervoltage lockout ? total solution size of less than 25mm 2 ? available in a 20-pin nanofree ? (csp) applications ? single/dual/triple white led flash supply for cell phones and smart-phones ? video lighting for digital video applications ? general lighting applications ? audio amplifier power supply figure 1. typical application 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 nanofree is a trademark of texas instruments. 3 i 2 c is a trademark of nxp semiconductors. production data information is current as of publication date. copyright ? 2010 ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. vout avin sw c i sw led1 pgnd pgnd agnd l 2.2 m h sda scl i 2 c i/f TPS61310 led2 led3 d1 d2 2.5 v..5.5 v strb0 ts nreset gpio/pg indled privacy indicator ntc tx-mask strb1 c o 10 m f 4.7 m f agnd
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. table 1. available options part number (1) package marking package device specific features (2) TPS61310yff TPS61310 up to 1750 ma (typ.) input valley current csp-20 tps61311yff tps61311 up to 2480 ma (typ.) input valley current (1) the yff package is available in tape and reel. add r suffix (tps6131xyffr) to order quantities of 3000 parts per reel, t suffix for 250 parts per reel. (2) for more details, refer to the section application diagrams . absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) value unit voltage range on avin, vout, sw, led1, led2, led3 (2) ? 0.3 to 7 v v i voltage range on scl, sda, strb0, strb1, nreset, gpio/pg (2) ? 0.3 to 7 v voltage range on tx-mask, ts (2) ? 0.3 to 7 v current on gpio/pg 25 ma power dissipation internally limited t a (3) operating ambient temperature range ? 40 to 85 c t j (max) maximum operating junction temperature 150 c t stg storage temperature range ? 65 to 150 c human body model 2 kv esd rating (4) charge device model 500 v machine model 100 v (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature [t a(max) ] is dependent on the maximum operating junction temperature [t j(max) ], the maximum power dissipation of the device in the application [p d(max) ], and the junction-to-ambient thermal resistance of the part/package in the application ( ja ), as given by the following equation: t a(max) = t j(max) ? ( ja p d(max) ) (4) the human body model is a 100-pf capacitor discharged through a 1.5k ? resistor into each pin. the machine model is a 200-pf capacitor discharged directly into each pin. dissipation ratings package thermal resistance (1) thermal resistance (1) power rating derating factor ja jb t a = 25 c above (2) t a = 25 c yff 71 c/w 21 c/w 1.4 w 14mw/ c (1) simulated with high-k board (2) maximum power dissipation is a function of t j (max), ja and t a . the maximum allowable power dissipation at any allowable ambient temperature is p d = (t j(max) ? t a )/ ja . 2 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 electrical characteristics unless otherwise noted the specification applies for v in = 3.6v over an operating junction temp. ? 40 c t j 125 c; circuit of parameter measurement information section (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit supply current v in input voltage range 2.5 5.5 v i out = 0 ma, device not switching (power safe mode) 590 700 a ? 40 c t j +85 c i q operating quiescent current into avin i out(dc) = 0ma, pwm operation ma 11.3 v out = 4.95v, voltage regulation mode i sd shutdown current ? 40 c t j +85 c 1 5 a v uvlo undervoltage lockout threshold v in falling 2.3 2.4 v (analog circuitry) output current regulation mode vin 5.5 v output voltage range voltage regulation mode 3.825 5.7 v v out internal feedback voltage accuracy 2.5v v in 4.8v, ? 20 c t j +125 c ? 2% 2% boost mode, pwm voltage regulation power-save mode ripple voltage i out = 10 ma 0.015 v out v p-p v out rising, 0000 ov[3:0] 0100 4.5 4.65 4.8 v output overvoltage protection ovp v out rising, 0101 ov[3:0] 1111 5.8 6.0 6.2 v output overvoltage protection hysteresis v out falling 0.15 v power switch r ds(on) switch mosfet on-resistance v out = v gs = 3.6 v 90 m ? rectifier mosfet on-resistance v out = v gs = 3.6 v 135 m ? i lkg(sw) leakage into sw v out = 0v, sw = 3.6v, ? 40 c t j +85 c 0.3 4 a vout = 4.95v i lim rectifier valley current limit (open-loop) ? 20 c t j +85 c ? 15 +15 % pwm operation, relative to selected ilim oscillator f osc oscillator frequency 1.92 mhz f acc oscillator frequency ? 10 +7 % thermal shutdown, hot die detector thermal shutdown (1) 140 160 c thermal shutdown hysteresis (1) 20 c hot die detector accuracy (1) ? 8 8 c (1) verified by characterization. not tested in production. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 3 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com electrical characteristics (continued) unless otherwise noted the specification applies for v in = 3.6v over an operating junction temp. ? 40 c t j 125 c; circuit of parameter measurement information section (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit led current regulator 0.4v v led1/3 2.0v, ? 10 +10 % 0ma i led1/3 100ma, t j = +85 c led1/3 current accuracy (1) 0.4v v led1/3 2.0v, ? 7.5 +7.5 % 100ma < i led1/3 400ma, t j = +85 c 0.4v v led2 2.0v, ? 10 +10 % 0ma i led2 250ma, t j = +85 c led2 current accuracy (1) 0.4v v led2 2.0v, ? 7.5 +7.5 % 250ma i led2 800ma, t j = +85 c led1/3 current matching (1) ? 10 +10 % led1/2/3 current temperature 0.05 %/ c coefficient 1.5v (v in -v indled ) 2.5v indled current accuracy ? 20 +20 % 2.6ma i indled 15.8ma, t j = +25 c indled current temperature 0.05 %/ c coefficient led1/2/3 sense voltage i led1-3 = full-scale current 400 mv v do vout dropout voltage i out = -15.8ma, t j = +25 c, device not switching 250 mv led1/2/3 input leakage current v led1/2/3 = v out = 5v, ? 40 c t j +85 c 0.1 4 a indled input leakage current v indled = 0v, ? 40 c t j +85 c 0.1 1 a led temperature monitoring i o(ts) temperature sense current source thermistor bias current 23.8 a ts resistance (warning ledwarn bit = 1 39 44.5 50 k ? temperature) ts resistance (hot temperature) ledhot bit = 1 12.5 14.5 16.5 k ? sda, scl, gpio/pg, tx-mask, strb0, strb1, nreset v (ih) high-level input voltage 1.2 v v (il) low-level input voltage 0.4 v low-level output voltage (sda) i ol = 8ma 0.3 v v (ol) low-level output voltage (gpio) dir = 1, i ol = 5ma 0.3 v v (oh) high-level output voltage (gpio) dir = 1, gpiotype = 0, i oh = 8ma v in ? 0.4 v i (lkg) logic input leakage current input connected to vin or gnd, ? 40 c t j +85 c 0.01 0.1 a strb0, strb1 pull-down resistance strb0, strb1 0.4 v 400 k ? r pd nreset pull-down resistance nreset 0.4 v 400 k ? tx-mask pull-down resistance tx-mask 0.4 v 400 k ? sda input capacitance sda = vin or gnd 9 pf scl input capacitance scl = vin or gnd 4 pf gpio/pg input capacitance dir = 0, gpio/pg = vin or gnd 9 pf c (in) strb0 input capacitance strb0 = vin or gnd 3 pf strb1 input capacitance strb1 = vin or gnd 3 pf nreset input capacitance nreset = vin or gnd 3.5 pf tx-mask input capacitance tx-mask = vin or gnd 4 pf (1) verified by characterization. not tested in production. 4 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 electrical characteristics (continued) unless otherwise noted the specification applies for v in = 3.6v over an operating junction temp. ? 40 c t j 125 c; circuit of parameter measurement information section (unless otherwise noted). typical values are for t j = 25 c. parameter test conditions min typ max unit timing t nreset reset pulse width 10 s from shutdown into video light mode start-up time 1.2 ms i led = 150ma led current settling time (1) triggered mode_ctrl[1:0] = 10 500 s by a rising edge on strb0 i led2 = from 0ma to 950ma led current settling time (1) triggered mode_ctrl[1:0] = 10 20 s by tx-mask i led2 = from 950ma to 150ma (1) settling time to 15% of the target value. i 2 c interface timing characteristics (1) parameter test conditions min max unit standard mode 100 khz fast mode 400 khz high-speed mode (write operation), c b ? 100pf max 3.4 mhz f (scl) scl clock frequency high-speed mode (read operation), c b ? 100pf max 3.4 mhz high-speed mode (write operation), c b ? 400pf max 1.7 mhz high-speed mode (read operation), c b ? 400pf max 1.7 mhz standard mode 4.7 s bus free time between a stop and t buf start condition fast mode 1.3 s standard mode 4 s hold time (repeated) start t hd , t sta fast mode 600 ns condition high-speed mode 160 ns standard mode 4.7 s fast mode 1.3 s t low low period of the scl clock high-speed mode, c b ? 100pf max 160 ns high-speed mode, c b ? 400pf max 320 ns standard mode 4 s fast mode 600 ns t high high period of the scl clock high-speed mode, c b ? 100pf max 60 ns high-speed mode, c b ? 400pf max 120 ns standard mode 4.7 s setup time for a repeated start t su , t sta fast mode 600 ns condition high-speed mode 160 ns standard mode 250 ns t su , t dat data setup time fast mode 100 ns high-speed mode 10 ns standard mode 0 3.45 s fast mode 0 0.9 s t hd , t dat data hold time high-speed mode, c b ? 100pf max 0 70 ns high-speed mode, c b ? 400pf max 0 150 ns standard mode 20 + 0.1 c b 1000 ns fast mode 20 + 0.1 c b 300 ns t rcl rise time of scl signal high-speed mode, c b ? 100pf max 10 40 ns high-speed mode, c b ? 400pf max 20 80 ns (1) specified by design. not tested in production. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 5 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com i 2 c interface timing characteristics (1) (continued) parameter test conditions min max unit standard mode 20 + 0.1 c b 1000 ns rise time of scl signal after a fast mode 20 + 0.1 c b 300 ns t rcl1 repeated start condition and after high-speed mode, c b ? 100pf max 10 80 ns an acknowledge bit high-speed mode, c b ? 400pf max 20 160 ns standard mode 20 + 0.1 c b 300 ns fast mode 20 + 0.1 c b 300 ns t fcl fall time of scl signal high-speed mode, c b ? 100pf max 10 40 ns high-speed mode, c b ? 400pf max 20 80 ns standard mode 20 + 0.1 c b 1000 ns fast mode 20 + 0.1 c b 300 ns t rda rise time of sda signal high-speed mode, c b ? 100pf max 10 80 ns high-speed mode, c b ? 400pf max 20 160 ns standard mode 20 + 0.1 c b 300 ns fast mode 20 + 0.1 c b 300 ns t fda fall time of sda signal high-speed mode, c b ? 100pf max 10 80 ns high-speed mode, c b ? 400pf max 20 160 ns standard mode 4 s t su , t sto setup time for stop condition fast mode 600 ns high-speed mode 160 ns c b capacitive load for sda and scl 400 pf i 2 c timing diagrams figure 2. serial interface timing for f/s-mode figure 3. serial interface timing for h/s-mode 6 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 sr p sr t fda t rda t hd;dat t su;sta t hd;sta t su;dat t su;sto t rcl1 t fcl t high t low t low t high t rcl t rcl1 = mcs current source pull-up = r (p) resistor pull-up sdah sclh note a: first rising edge of the sclh signal after sr and after each acknowledge bit. see note a see note a t f t low t r t hd;sta t hd;dat t su;dat t f high t su;sta s sr p s t hd;sta t r t buf t su;sto sda scl
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 device information table 2. pin functions pin i/o description name no. avin e4 i this is the input voltage pin of the device. connect directly to the input bypass capacitor. vout a2 o this is the output voltage pin of the converter. led1 e2 i led return input (current sinks). this feedback pin regulates the led current through the internal sense led2 e1 i resistor by regulating the voltage across it. connect to the cathode of the white leds. led3 e3 i strb0 b4 i led1/2/3 enable logic input. this pin can be used to enable/disable the high-power leds connected to the device. strb0 = low: led1, led2 and led3 current regulators are turned off. strb0 = high: led2, led2 and led3 current regulators are active. the led current level (video light or flash current) is defined according to the strb1 logic level. nreset b3 i master hardware reset input. nreset = low: the device is forced in shutdown mode and the i 2 c control i/f and all internal control registers are reset. nreset = high: the device is operating normally under the control of the i 2 c interface. scl b2 i serial interface clock line. this pin must not be left floating and must be terminated. sda b1 i/o serial interface address/data line. this pin must not be left floating and must be terminated. gpio/pg d4 i/o this pin can either be configured as a general purpose input/output pin (gpio) or either as an open-drain or a push-pull output to signal when the converters output voltage is within the regulation limits (pg). per default, the pin is configured as an open-drain power-good output. ts c4 i ntc resistor connection. this pin can be used to monitor the led temperature. connect a 220k ? ntc resistor from the ts input to ground. in case this functionality is not desired, the ts input should be tied to avin or left floating. indled a1 o this pin provides a constant current source to drive low v f leds. connect to led anode. strb1 d3 i led current level selection input. pulling this input high disables the video light watchdog timer. strb1 = low: flash mode is enabled. strb1 = high: video light mode is enabled. tx-mask c3 i rf pa synchronization control input. pulling this pin high turns the led from flash to video light operation, thereby reducing almost instantaneously the peak current loading from the battery. sw c1 i/o inductor connection. drain of the internal power mosfet. connect to the switched side of the inductor. sw c2 is high impedance during shutdown. pgnd d1 power ground. connect to agnd underneath ic. d2 agnd a3 analog ground. a4 figure 4. pin assignments copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 7 product folder links: TPS61310 tps61311 e4 e3 e2 e1 d4 d3 d2 d1 c4 c3 c2 c1 b4 b3 b2 b1 a4 a3 a2 a1 a4 a3 a2 a1 b4 b3 b2 b1 c4 c3 c2 c1 d4 d3 d2 d1 e4 e3 e2 e1 csp-20 (top view) csp-20 (bottom view)
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com functional block diagram 8 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 avin vout sw led2 ref scl sda i 2 ci/f agnd pgnd strb1 currentcontrol p p sensefb comparator error amplifier ovp comparator voltage regulation current regulation v ref on/off control logic maxt on timer dac t on control backgate control led1 currentcontrol low-sideledcurrentregulator p sensefb on/off p led3 vledsense dac sensefb strb0 tx-mask indled avin indc[1:0] high-sideledcurrentregulator slew-rate controller nreset ledcurrentramp r s q q control logic ts avin 23a v ref = 1.05v v ref = 0.345v warning hot undervoltage lockout biassupply bandgap hotdie indicator v ref =1.238v 350 k battery droop threshold digital filter vbat droop comparator oscillator (stop)
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 timer block diagram parameter measurement information list of components: l = 2.2 h, wuerth elektronik we-tpc series c i , c o = 10 f 6.3v x5r 0603 ? tdk c1605x5r0j106mt ntc = 220k ? , murata ncp18wm224j03rb copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 9 product folder links: TPS61310 tps61311 vout avin sw c i sw led1 pgnd pgnd agnd l 2.2 m h sda scl i 2 c i/f TPS61310 led2 led3 d1 d2 2.5 v..5.5 v strb0 ts nreset gpio/pg indled privacy indicator ntc tx-mask strb1 c o 10 m f 4.7 m f agnd 16-bit prescaler safety timer time-out (to) dimming (dim) timer value (stim) strb0 t pulse clock edge detect start mode 0 current regulator mode C dc light / flash active mode 0 = low mode 1 = high duty-cycle generator (5% ... 67%) led1-3 on/off control 0: led1-3 off 1: dc light current level start flash/timer (sft) tx-mask 0: dc light current level 1: flash current level led1-3 current control 350 k w safety timer trigger (stt) 1 01 gpio/pg (gpio bit) port direction (dir) (gpio bit) pwrok port type (pg) dc light safety timer (11.2s) mode 1 mode 0 0: normal operation 1: disable current sink 350 k w strb1 mode 1
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com typical characteristics table of graphs figure led power efficiency vs. input voltage figure 5, figure 6 dc input current vs. input voltage figure 7 led current vs. led pin headroom voltage figure 8, figure 9 figure 10, figure 11, led current vs. led current digital code figure 12, figure 13 indled current vs. led pin headroom voltage figure 14 voltage mode efficiency vs. output current figure 15, figure 16 dc output voltage vs. output current figure 17, figure 18 maximum output current vs. input voltage figure 19 dc pre-charge current vs. differential input-output voltage figure 20, figure 21 supply current vs. input voltage figure 22 temperature detection threshold figure 23, figure 24 junction temperature vs. port voltage figure 25 flash sequence figure 26 figure 27, figure 28, tx-masking operation figure 29 low-light dimming mode operation figure 30 pwm operation figure 31 pfm operation figure 32 down-mode operation (voltage mode) figure 33 voltage mode load transient response figure 34 start-up into video light operation figure 35 start-up into voltage mode operation figure 36 figure 5. led power efficiency figure 6. led power efficiency vs. vs. input voltage input voltage 10 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 0 10 20 30 40 50 60 70 80 90 100 led power efficiency (pled/pin) - % 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i iled1 = 50 ma iled2 = 100 ma iled3 = i = 1750 ma, tx-mask = low lim iled1 = 0 ma iled2 = 200 ma iled3 = 10 iled1 = 5 ma iled2 = 150 ma iled3 = 7 iled1 = 50 ma iled2 = 550 ma iled3 = 2 iled1 = 50 ma iled2 = 600 ma iled3 = 3 iled1 = 50 ma iled2 = 450 ma iled3 = 2 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i 0 10 20 30 40 50 60 70 80 90 100 led power efficiency (pled/pin) - % iled2 = 75 ma iled2 = 100 ma iled2 = 150 ma iled2 = 225 ma i = 1750 ma, tx-mask = low led2 channel lim
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 typical characteristics (continued) figure 7. dc input current figure 8. led2 current vs. vs. input voltage led2 pin headroom voltage figure 9. led1+led3 current figure 10. led2 current vs. vs. led1+led3 pin headroom voltage led2 current digital code copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 11 product folder links: TPS61310 tps61311 0 100 200 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 1100 1200 1300 1400 led1, led3 pin headroom voltage - mv led1 + led3 current - ma iled1 = iled3 = 400 ma i = 1750 ma lim iled1 = iled3 = 350 ma iled1 = iled3 = 300 ma iled1 = iled3 = 250 ma 0 25 50 75 100 125 150 175 200 225 250 275 300 0 25 50 75 100 125 150 175 200 225 250 275 300 led2 current digital code - ma v = 2.5 v in v = 4.5 v in v = 3.6 v in led2 current - ma i = 1750 ma lim 0 100 200 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 1100 1200 1300 1400 led2 pin headroom voltage - mv iled2 = 800 ma iled2 = 700 ma iled2 = 550 ma iled2 = 300 ma iled2 = 450 ma iled2 = 350 ma i = 1750 ma lim led2 current - ma 0 250 500 750 1000 1250 1500 1750 2000 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i = 1750 ma, tx-mask = low lim iled1 = 50 ma iled2 = 550 ma iled3 = 2 iled1 = 50 ma iled2 = 600 ma iled3 = 3 iled1 = 50 ma iled2 = 450 ma iled3 = 2 iled1 = 50 ma iled2 = 275 ma iled3 = 2 dc input current - ma
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com typical characteristics (continued) figure 11. led1, led3 current figure 12. led2 current vs. vs. led1, led3 current digital code led2 current digital code figure 13. led1, led3 current figure 14. indled current vs. vs. led1, led3 current digital code indled pin headroom voltage 12 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 200 225 250 275 300 325 350 375 400 425 450 200 225 250 275 300 325 350 375 400 425 450 led1, led3 current digital code - ma v = 4.5 v in v = 3.6 v in v = 2.5 v in i = 1750 ma lim led1, led3 current - ma 0 1 2 3 4 5 6 7 8 9 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 indled pin headroom voltage - v indled current - ma indled = 0011 indled = 0010 indled = 0001 t = 85c a t = 25c a t = -40c a t = 85c a t = 25c a t = -40c a t = 85c a t = 25c a v = 3.6 v in t = -40c a 25 50 75 100 125 25 50 75 100 125 led1, led3 current digital code - ma v = 4.5 v in v = 3.6 v in v = 2.5 v in led1, led3 current - ma i = 1750 ma lim 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 led2 current digital code - ma v = 4.5 v in v = 3.6 v in i = 1750 ma lim 200 300 400 500 600 700 800 900 v = 2.5 v in led2 current - ma
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 typical characteristics (continued) figure 15. efficiency figure 16. efficiency vs. vs. output current output current figure 17. dc output voltage figure 18. dc output voltage vs. vs. load current load current copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 13 product folder links: TPS61310 tps61311 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 i - output current - ma o efficiency - % v = 4.2 v in v = 3.6 v in v = 2.5 v in v = 4.95 v voltage mode regulation out i = 1750 ma lim v = 3 v in pfm/pwm operation forced pwm operation 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 1 10 100 1000 10000 i - output current - ma o v - output voltage (dc) - v o voltage mode regulation forced pwm operation pfm/pwm operation v = 3.6 v in v = 2.5 v in v = 4.95 v, i = 1750 ma out lim v = 4.2 v in 3.71 3.749 3.787 3.825 3.863 3.902 3.94 3.978 4.016 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 i - output current - ma o v - output voltage (dc) - v o i = 0 ma out i = 100 ma out i = 1000 ma out voltage mode regulation v = 3.825 v out i = 1750 ma lim 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 i - output current - ma o efficiency - % forced pwm operation pfm/pwm operation v = 4.2 v in v = 3.6 v in v = 2.5 v in v = 3 v in v = 3.825 v voltage mode regulation out i = 1750 ma lim
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com typical characteristics (continued) figure 19. maximum output current figure 20. dc pre-charge current vs. vs. input voltage differential input-output voltage figure 21. dc pre-charge current figure 22. supply current vs. vs. differential input-output voltage input voltage 14 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 0 50 100 150 200 250 300 350 400 0 0.6 1.2 1.8 2.4 3 3.6 4.2 differential input - output voltage - v v = 3.6 v, t = -40c in a v = 3.6 v, t = 25c in a v = 3.6 v, t = 85c in a dc pre-charge current - ma 1000 500 600 700 800 900 1100 1200 1300 1400 1500 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i - supply current - a cc m v = 5.7 v, t = 25c out a v = 3.825 v, t = 25c out a v = 4.95 v, t = 25c out a v = 4.95 v, t = 85c out a v = 4.95 v, t = -40c out a i = 0 ma enpsm bit = envm bit = 1 out 0 50 100 150 200 250 300 350 400 0 0.6 1.2 1.8 2.4 3 3.6 4.2 differential input - output voltage - v v = 3.6 v, t = 25c in a v = 2.5 v, t = 25c in a v = 4.2 v, t = 25c in a dc pre-charge current - ma 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v - input voltage - v i i - output current (max) - ma o v = 4.95 v, i = 1250 ma out lim voltage mode regulation v = 5.7 v, i = 1250 ma out lim
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 typical characteristics (continued) figure 23. temperature detection threshold figure 24. temperature detection threshold figure 25. junction temperature vs. port voltage copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 15 product folder links: TPS61310 tps61311 -50 -25 0 25 50 75 100 125 150 175 200 -0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 port voltage - v t - junction temperature - c j v port port input buffer 100 a m i = -100 a port m strb1 input tx-mask input 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 64 65 66 67 68 69 70 71 72 73 74 75 temperature detection (70c threshold) sample percentage - % v = 3.6 v in sample size = 76 0 2 4 6 8 10 12 14 16 18 20 22 24 26 50 51 52 53 54 55 56 57 58 59 60 temperature detection (55c threshold) sample percentage - % v = 3.6 v in sample size = 76
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com typical characteristics (continued) figure 26. flash sequence (strb1=0) figure 27. tx-masking operation (strb1=0) figure 28. tx-masking operation (strb1=0) figure 29. tx-masking operation (strb1=0) 16 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 t - time = 1 ms/div i(500ma/div) led2 v = 3.6v, v = 4.95v, i = 1750ma in out lim led2 channel onlydclc2[2:0] = 000 fc2[5:0] = 100000 strb0(2v/div) led2 pin headroom voltage (1v/div) v(1v/div - 3.6v offset) out t - time = 5 s/div tx-mask(2v/div) i(200ma/div) led2 i(200ma/div) l v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel only dclc2[2:0] = 111 fc2[5:0] = 100000 t - time = 100 s/div tx-mask(2v/div) i(200ma/div) led2 i(500ma/div) l v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel onlydclc2[2:0] = 010 fc2[5:0] = 100000 t - time = 500 s/div tx-mask(2v/div) i(200ma/div) led2 v = 3.6v, v = 4.95v, i = 1750ma in out lim dclc2[2:0] = 000 fc2[5:0] = 011000 strb0(2v/div) i + (200ma/div) led1 i led3 dclc13[2:0] = 000 fc13[4:0] = 01100
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 typical characteristics (continued) figure 30. low-light dimming mode operation figure 31. pwm operation figure 32. pfm operation figure 33. down-mode operation (voltage mode) copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 17 product folder links: TPS61310 tps61311 t - time = 2 s/div m sw(5v/div) i(200ma/div) l v(100mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 50ma, i = 1750ma out out lim pfm/pwm operationenpsm bit = 1 t - time = 2 s/div m sw(5v/div) i(200ma/div) l v(100mv/div - 3.825v offset) out v = 4.2v, in v = 3.825v i = 50ma, i = 1750ma out out lim pfm/pwm operationenpsm bit = 1 i(20 ma/div) led2 t - time = 10 s/div frequency = 30 khzduty cycle = 23 % t - time = 125 ns/div sw(2v/div) i(200ma/div) l v(20mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 300ma, i = 1750ma out out lim forced pwm operationenpsm bit = 0
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com typical characteristics (continued) figure 34. voltage mode load transient response figure 35. start-up into video light operation figure 36. start-up into voltage mode operation 18 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 t - time = 100 s/div envm bit voltage mode regulation start i(200ma/div) l v = 3.6v, v = 4.95v i = 1750ma in out lim i = 0ma, out v(2v/div) out t - time = 50 s/div m i(500ma/div) l v(500mv/div - 4.95v offset) out v = 3.6v, in v = 4.95v i = 1750ma out lim pfm/pwm operationenpsm bit = 1 i(500ma/div) out 50ma to 500ma load step t - time = 200 s/div mode_ctrl[1:0] = 01 dc light turn-on i(50ma/div) led2 i(200ma/div) l v = 3.6v, v = 4.95v i = 1750ma in out lim led2 channel onlydclc2[2:0] = 100 v(2v/div) out
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 detailed description ? operation ? video light and flash operation ? voltage mode ? privacy indicator ? safe operation and protection features ? power-save mode operation, efficiency ? start-up sequence ? nreset input: hardware enable / disable ? shutdown ? serial interface description operation the tps6131x family is an integrated solution with a wide feature set for driving up to three leds for still-camera flash and video-camera lighting applications. it employs a 2mhz fixed on-time, pwm current-mode converter to generate the output voltage required to drive up to three high-power leds in parallel. the device integrates an nmos-switch power stage and a synchronous pmos rectifier. the device also implements a set of linear low- side current regulators to control the led current when the battery voltage is higher than the diode forward voltage. the high efficiency boost converter stage and led forward voltage adoption ensure lowest device input current for a given led output current. a special circuit disconnects the load from the battery during shutdown of the converter. in conventional synchronous-rectifier circuits, the back-gate diode of the high-side pmos is forward biased in shutdown, allowing current to flow from the battery to the output. the tps6131x prevents this by disconnecting the cathode of the back-gate diode of the high-side pmos from the source when the regulator is in shutdown. the tps6131x device not only operates as a regulated current source, but also as a standard voltage-boost regulator featuring a power-save mode for improved efficiency at light loads. if the input voltage is higher than the programmed output voltage, a down mode is implemented that acts similarly to an ldo. the power stage is capable of supplying a maximum total current of roughly 1500ma. the tps6131x provides three constant-current sinks, capable of sinking up to 2x 400ma (led1 and led3) and 800ma (led2) in flash mode. figure 37. tps6131x states special effort is taken for safe operation and robust system integration. the battery voltage can be monitored so that the flash current is not increased if the battery voltage drops by a programmable threshold. internal timers limit the flash on-time to prevent potential camera-engine software errors, and a video light watchdog acts in a similar fashion. multiple monitoring features (led and die temperature, input voltage droop etc.) keep the device and leds operating properly. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 19 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com the tps6131x integrates an i 2 c compatible interface allowing transfers up to 3.4mbits/s for controlling the device, featuring low-speed mode, standard mode and high-speed mode compatible operation. additionally, basic functions can be triggered by dedicated hardware input signals, such as strb0 and strb1 for triggering the flash or video lighting with zero latency. video light and flash strobe operation the tps6131x devices drive one, two or three leds for video light and flash application. the video light and flash operation can either be triggered by an i 2 c software command or by means of dedicated, zero latency hardware signals. led hardware setup the tps6131x device utilizes led forward-voltage sensing circuitry on led1-3 pins to optimize the power-stage boost ratio for maximum efficiency. due to the nature of the sensing circuitry, it is not recommended to leave any of the led1-3 pins unused if the operation has been selected via enled[3:1] bits. leaving led1-3 pins unconnected, while the respective enledx bits have been set, forces the control loop into high gain, and eventually trips the output overvoltage protection. figure 38 shows the recommend led setup for a single, dual or triple-led application. figure 38. white led hardware setup options the led1-3 inputs may be connected together to drive one or two leds at higher currents. connecting the current sink inputs in parallel does not affect the internal operation of the tps6131x. for best operation, it is recommended to disable the led inputs that are not connected. (see the enled[3:1] bits description in register5 description ). the video light currents are individually programmed via the video light control bits dcl13[2:0] and dcl2[2:0] , the flash currents via fc2[5:0] and fc13[4:0] bits accordingly. if, for single or dual led application as shown in figure 38 , current sinks are connected to each other and enabled, the resulting video / flash current will be the sum of the programmed currents. triggering video light and flash for most flexible system integration, the tps6131x offers several options for activating the video light and flash. depending on the settings of the mode_ctrl[1:0] bits, the device can enter different modes of operation. it offers the option of triggering the video light and flash via hardware signals (strb0, strb1) or software i 2 c command. the flash-signal hardware trigger can be on the leading-edge, turning on for the programmed flash on time, or level sensitive, turning on for as long as the signal is logic high. the tps6131x flash timer is programmed via the stim[2:0] and selstim bits. if the flash is fired by a rising- edge trigger or by an i 2 c command, the timer defines the flash duration. if the flash is fired by a level-sensitive trigger, the timer defines the maximum flash-on duration, and overrides the hardware signal if the programmed on-time is exceeded. 20 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 tps6131x vout c out led1 led2 led3 tps6131x vout c out led1 led2 led3 tps6131x vout c out led1 led2 led3 single led dual led tripple led
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 for video lighting, a watchdog timer is implemented; this must be refreshed within 13.0 seconds. this function can be disabled, as described below. mode_ctrl[1:0] = 01 the strb0, strb1 inputs are disabled. the device regulates the led current in video light mode (dclc bits) regardless of the strb0, strb1 inputs and the start_flash/timer (sft) bit. to avoid device shutdown because of the video light safety timeout, mode_ctrl[1:0] must be refreshed within less than 13.0 seconds (strb1 = 0). the video light watchdog timer can be disabled by pulling the strb1 signal high. mode_ctrl[1:0] = 10 the strb0, strb1 inputs are enabled. the flash pulse can be triggered by these synchronization signals, or by a software command (start_flash/timer (sft) bit). the leds are enabled/disabled according to the strb0, strb1 input. the flash safety timer is activated, and the video light watchdog timer is disabled. the dual-wire camera-module interface strb0 and strb1 inputs are used for selecting the video light (strb1 = 1) or flash (strb1 = 0) mode. the strb0 signal then triggers the video light or flash, depending on the state of strb1. the stt bit defines if the flash trigger is level sensitive (stt = 0), or fired on the rising edge (stt = 1). level-sensitive flash trigger (stt = 0) in this mode, the high-power leds are driven at the flash-current level and the safety timer (stim) is running. the maximum duration of the flash pulse is defined in the stim[2:0] register. the safety timer is triggered on rising edge and stopped by a negative logic on the synchronization source (strb0, strb1 = 0) or by a timeout event (to bit). figure 39. hardware synchronized video light and flash strobe rising-edge flash trigger (stt = 1) in this mode, the high-power leds are driven at the flash current level and the safety timer (stim) is running. the duration of the flash pulse is defined in the stim[2:0] register. the flash strobe is started either by a rising edge on the synchronization source (strb0 = 1, strb1 = 0) or by a positive transition on the start-flash/timer (sft) bit (strb0 = 1, strb1 = 0). once running, the timer ignores all kind of triggering signals and only stops after a timeout (to). start-flash/timer (sft) bit is being reset by the timeout (to) signal. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 21 product folder links: TPS61310 tps61311 strb0 af assist light strobe strb1 timer duration < stim led control dc light flash led off led off led off
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com figure 40. edge sensitive timer (single trigger event) voltage mode in this mode, the tps6131x operates as a standard voltage-boost regulator, featuring power-save mode for improved efficiency under light loads. the voltage-mode operation is enabled by software control by setting the mode-control bit mode_ctrl[1:0] = 11. the device regulates a constant output voltage according to the ov[3:0] bit settings (between 3.825v and 5.7v in 125mv steps). in voltage mode, the led current sinks led1-3 are turned off. the tps6131x integrates a software control bit (envm bit) that can be used to force the converter to run in voltage mode. this enables the converter to operate at a fixed programmed output voltage (according to the ov[3:0] settings) while operating the leds. table 3 provides an overview of the different voltage mode variations. table 3. voltage mode description internal register envm operating modes settings mode_ctrl[1:0] bit 11 0 leds are turned off and the converter operate in voltage-regulation mode (vm); the output voltage is set via register ov[3:0]. 00 1 01 1 the converter operates in voltage-regulation mode (vm); the output voltage is set via the register ov[3:0]. the leds are turned-on for video light operation and the energy is being directly transferred from the battery to the output. the led currents are regulated by the means of the low-side current sinks. 10 1 the converter operates in the voltage-regulation mode (vm); the output voltage is set via the register ov[3:0]. the led currents are regulated by the low-side current sinks. the leds are ready for flash operation. 11 1 leds are turned off and the converter operates in the voltage regulation mode (vm); the output voltage is set via the register ov[3:0]. down mode in voltage mode operation in general, a boost converter only regulates output voltages which are higher than the input voltage. the tps6131x can regulate 4.2v at the output with an input voltage as high as 5.5v. to control these applications properly, a down-conversion mode is implemented. in voltage-regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to down-conversion mode. in this mode, the control circuit changes the behavior of the rectifying pmos. it sets the voltage drop across the pmos as high as needed to regulate the output voltage. this increases the power losses in the converter, and must be taken into account for thermal design. the down-conversion mode is automatically turned off as soon as the input voltage falls to approximately 200mv below the output voltage. for proper operation in down-conversion mode the output voltage should not be programmed higher than approximately 5.3v. care should be taken not to violate the absolute maximum ratings at the sw pins. 22 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 strb0 af assist light strobe strb1 timer duration = stim led control dc light flash led off led off led off
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 power good indication the tps6131x integrates a power-good circuit that is activated when the device operates in voltage-regulation mode (mode_ctrl[1:0] = 11 or envm = 1). in shutdown mode (mode_ctrl[1:0] = 00, envm = 0), the gpio/pg pin state is defined below, according to the gpiotype bit: gpiotype gpio/pg shutdown state 0 reset/pulled to ground 1 open-drain depending on the gpio/pg output stage type selection (i.e., push-pull or open-drain), the polarity of the power- good output signal (pg) can be inverted or not. the power-good software bit and hardware signal polarity is defined below: gpiotype pg bit gpio/pg output port comments 0 0 0: push-pull output output is active-high 1 1 0 open-drain 1: open-drain output output is active-low 1 low the power-good signal is true when the output voltage is within ? 1.5% and +2.5% of its nominal value. conversely, it is false when the voltage-mode operation is suspended (mode_ctrl[1:0] 11 and envm = 0). figure 41. power good operation (dir = 1, gpiotype = 1) the tps6131x device uses a control architecture that ? recycles ? excess energy that might be stored in the output capacitor. by reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source. in this case, the power-good signal is de-asserted while the output voltage is decreasing towards its target value (i.e., the closest fit voltage the converter can support. privacy indicator the privacy indicator functionality can be used to indicate when a person is being photographed or filmed. the tps6131x device offers two options of privacy indication: a dedicated pin driving an additional privacy indicator led or using the white leds with pulse width modulation. dedicated led privacy indicator the tps6131x device provides a high-side linear constant current source to drive low v f leds. the led current is directly regulated off the battery and can be controlled via the indc[3:0] bits, ranging 2.6ma to 15.8ma in 7 programable current steps. the device can drive two possible hardware configurations shown in figure 42 and figure 43 . in figure 42 the tps6131x device drives a privacy indicator led towards ground. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 23 product folder links: TPS61310 tps61311 voltage mode request output voltage, v out nom. voltage start-up phase power good bit, (pg) power good output, gpio/pg hi-z hi-z 1.025 v out (nom ) 0.985 v out (nom ) v out (nom ) output voltage down regulation output voltage up regulation forced pwm mode operation forced pwm mode operation (pg) bit
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com figure 42. configuration 1 figure 43. configuration 2 the tps6131x device also allows a path for driving a privacy indicator led that is reverse biased to the white flash led, see figure 43 . to do so, the output of the converter (vout) is pulled to ground thus allowing a reverse current to flow. this mode of operation is only possible when the converter ? s power stage is in shutdown (mode_ctrl[1:0] = 00, envm = 0). white led privacy indicator the tps6131x device features white led drive capability at very low light intensity. to generate a reduced led average current, the device employs a 30khz fixed-frequency pwm modulation scheme. the pwm timer uses the internal oscillator as reference clock, therefore the pwm modulating frequency shows the same accuracy as the internal reference clock. operation is shown in the timer block diagram. the video light current is modulated with a duty cycle defined by the indc[3:0] bits. the low light dimming mode can only be activated in the software-,controlled video-light-only mode (mode_ctrl[1:0] = 01, envm = 1), and applies to the leds selected via enled[3:1] bits. in this mode, the video light safety-timeout feature is disabled. figure 44. pwm dimming principle safe operation and protection features led temperature monitoring (finger-burn protection) the tps6131x device optionally monitors the led temperature. critical temperatures are handled in two stages reflected by two bits: ledwarn provides an early warning to the camera engine, ledhot immediately suspends the flash operation. the led temperature is sensed by measuring the voltage drop of a negative-temperature-coefficient resistor connected between the ts and agnd pins. an internal current source provides the bias (c.a. 24 a) for the ntc, and the ts pin voltage is compared to internal thresholds (1.05v and 0.345v) to protect the leds against overheating. see the application information section for choosing the ntc. the temperature-monitoring blocks are explicitly active in video light or flash modes. in voltage-mode operation [mode_ctrl[1:0] = 11], the device only activates the ts input when the ents bit is set high. the ledwarn and ledhot bits reflect the led temperature. the ledwarn bit is set when the voltage at the ts pin is lower than 1.05v. this threshold corresponds to an led warning temperature value; device operation is still permitted. while regulating led current (i.e. video light or flash modes), the ledhot bit is latched when the voltage at the ts pin is lower than 0.345v. this threshold corresponds to an excessive led temperature value; device operation is immediately suspended, (mode_ctrl[1:0] bits are reset, and the hotdie[1:0] bits are set). 24 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 pwm dimming steps 5%, 11%, 17%, 23%, 30%, 36%, 48%, 67% i dclight 0 i led (dc ) = i dclight x pwm dimming step t 1 t pwm tps6131x vout c out indled led1 led2 led3 tps6131x vout c out indled led1 led2 led3
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 led failure modes (open / short detection) and overvoltage protection the tps6131x devices incorporate protection features to indicate if the connected led(s) are failing. these protections cover overvoltage conditions, which are caused by a failing led showing open circuit behavior, as well as short circuit conditions caused by a failing led or further reasons causing a short circuit condition. if such failure conditions occur, these are indicated by setting a failure detection flag. furthermore, the maximum current drawn from the output is limited and can be programmed by the current-limit setting. led open circuit detection / over voltage protection if the connected led(s) fail showing an open circuit behavior or are disconnected, the vout output voltage must be limited to prevent the step-up converter from exceeding critical values. an overvoltage protection is implemented to avoid the output voltage exceeding critical values for the device and possibly for the system it is supplying. for this protection the tps6131x output voltage is monitored internally. the tps6131x device limits v out according to the overvoltage protection settings (refer to ovp specification). in this failure mode, v out is either limited to 4.65v (typ.) or 6.0v (typ.) and the high-power led failure [hplf] flag is set. the ovp threshold depends on the programmed output voltage [ov]. ovp threshold operating conditions 4.65 v typ. 0000 ov[3:0] 0100 6.0 v typ. 0101 ov[3:0] 1111 short circuit protection the tps6131x devices incorporate double protection to protect the device and application circuit from short circuit conditions occurring between vout and the current sinks led1..3. if a short circuit condition occurs while the led(s) are operated, the low side current sinks led1, led2, led3 limit the maximum output current as programmed for the video-light mode or flash mode respectively. if a short circuit condition occurs, the current sinks increase their input resistance to prevent excessive current to be drawn. furthermore, the high-power led failure flag (hplf) is set to indicate the short circuit condition. (hplf) is triggered if the led forward voltage drops below 1.23v typically. the second protection is the current limit, which generally limits the current drawn from vout. see the current limit section . led current ramp-up/down to achieve smooth led current waveforms and avoid excessive battery voltage drop, the tps6131x device actively controls the led current ramp-up / down sequence. table 4. led current ramp-up/down control vs operating mode i step = 25ma led current ramp-up t rise = 12 s slew-rate 2.1ma/ s i step = 25ma led current ramp-down t fall = 0.5 s slew-rate 50ma/ s copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 25 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com figure 45. led current slew-rate control battery voltage droop monitoring and protection during a high-power flash strobe, the battery voltage usually drops by a few hundred millivolts. to prevent the battery voltage from collapsing too much, the tps6131x devices integrates a battery voltage droop monitoring feature to automatically limit the flash current if the battery voltage drops more than a programmable threshold. the battery voltage droop monitoring feature can be enabled/disabled via the enbatmon bit. at the very beginning of the flash strobe, the device measures the battery voltage and sets a minimum battery voltage threshold based on the tolerable droop (refer to batdroop[2:0] bits). while the led current is increasing to the target flash current (see fc13[4:0] and fc2[5:0] bits), a comparator monitors the actual battery voltage and stops the ramp-up sequence when the droop exceeds the limit. operation is understood best by referring to the functional block diagram and to figure 46 . the battery voltage droop monitor feature is automatically disabled during a tx-mask event. figure 46. battery voltage droop monitoring / led current control principle (strb1 = 0, tx-base = 1) undervoltage lockout the undervoltage lockout circuit prevents the device from error conditions at low input voltages. it prevents the converter from turning on the switch ? mosfet, or rectifier ? mosfet for battery voltages below 2.3v. the i 2 c compatible interface is fully functional down to 2.1v input voltage. hot die detection and thermal shutdown the tps6131x device offers two levels of die temperature monitoring and protection, which are hot die detection and thermal shutdown functionality. the hot die detector (hotdie[1:0] bits) reflects the instantaneous junction temperature. this functionality is always enabled except when the device is in shutdown mode. the hot die detector monitors the junction temperature but does not shut down the device. it provides an early warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown during the next high-power flash strobe. 26 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 maximum allowedbattery droop (batdroop[2:0]) dc light strb0 v bat i led target flash current (950ma) actual flash current (700ma) battery droopthreshold exceeded led current isstopped from ramping further led current time t rise i step t fall
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 as soon as the junction temperature t j exceeds 160 c typical, the device goes into thermal shutdown. in this mode, the power stage and the low-side current regulators are turned off, the hotdie[1:0] bits are set and can only be reset by a read access. in the voltage mode operation (mode_ctrl[1:0] = 11 or envm = 1), the device continues its operation when the junction temperature falls below 140 c typ. again. in the current regulation mode (i.e., video light or flash modes), device operation is suspended. table 5. die temperature bits hotdie[1:0] t j 00 < 55 c 01 55 c < = t j < = 70 c 10 > 70 c 11 thermal shutdown tripped. the bit is reset after read access current limit the tps6131x devices employ a programmable inductor-current limit. this allows choosing inductors with different saturation-current ratings. furthermore, this provides protection against a shorted inductor, or if the inductance value has dramatically dropped. this protects the battery from excessively-high current drain. the current limit circuit employs a valley current sensing scheme. the detection threshold is user selectable via the ilim bit. the ilim bit can only be set prior to entering operation, i.e. initial shutdown state. figure 47 illustrates the inductor and rectifier current waveforms during current limit operation. the output current, iout, is the average of the rectifier ripple current waveform. when the load current is increased such that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). both the output voltage and the switching frequency are reduced as the power stage of the device operates in a constant current mode. the maximum continuous output current (i out(cl) ), before entering current limit operation, can be defined as: (1) the tps6131x device also provides a negative current limit ( 300ma) to prevent an excessive reverse inductor current when the power stage sinks current from the output in the forced continuous-conduction mode. figure 47. inductor/rectifier currents in current limit operation copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 27 product folder links: TPS61310 tps61311 i in (dc) inductor current rectifier current d i l f d l v i in l = d i l current limit threshold i valley = i lim i in (dc) increased load current i out (cl) d i l f i peak i (= i ) out(dc) led out in in out(cl) valley l l out v v v 1 d i = (1 d) (i + i ) with i = and d 2 l f v - - d d ?
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com table 6. inductor current limit operation current limit setting ilim bit TPS61310 tps61311 1250 ma 1800 ma low 1750 ma 2480 ma high flash blanking (tx-mask) for instantaneous flash-current reduction the tps6131x devices offer a dedicated hardware signal input (tx-mask) that can be used to reduce the flash current to the programmed video light level instantaneously. this feature can be used to reduce the overall current drawn from the battery if other system components require high energy simultaneously, e.g. during a rf pa transmission pulse. the tx-mask function has no influence on the safety timer duration. figure 48. synchronized flash with blanking periods (strb1 = 0) power-save mode operation, efficiency the tps6131x integrates a power-save mode to improve efficiency under light loads. in power-save mode the converter only operates when the output voltage trips below a set threshold voltage. it ramps up the output voltage with one-to-several pulses and returns to power-save mode once the output voltage exceeds the set threshold voltage. figure 49. operation in pfm mode and transfer to pwm mode the power-save mode can be enabled and disabled via the enpsm bit. in down conversion mode, power-save mode is always active and the device cannot be forced into fixed frequency operation at light loads. the led sense voltage has a direct effect on converter efficiency. because the voltage across the low-side current regulator does not contribute to the output power (led brightness), the lower the sense voltage the higher the efficiency will be. 28 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 v out nom. pfm mode at light load pwm mode at heavy load pfm ripple about 0.015 x v out 1.013 x v out nom. output voltage flash dc light led currentstrb0 tx- mask
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 the integrated current control loop automatically selects the minimum boost ratio to maintain regulation based on the led forward voltage and current requirements. the low-side current regulators drop the voltage difference between the input voltage and the leds forward voltage (v f(led) < v in ). when running in boost mode (v f(led) > v in ), the voltage present at the led1-3 pins of the low-side current regulators is typically 400mv, leading to high power conversion efficiency. depending on the input voltage and the leds forward voltage characteristic the converter efficiency is approximately 75% to 90%. start-up sequence to avoid high inrush current during start-up, special care is taken to control the inrush current. when the device enables, the internal startup cycle starts with the first step, the pre-charge phase. during pre-charge, the rectifying switch is turned on until the output capacitor is either charged to a value close to the input voltage or 3.3v, whichever occurs first. the rectifying switch is current-limited during that phase. the current limit increases with decreasing input-to-output voltage difference. this circuit also limits the output current under output short-circuit conditions. after having pre-charged the output capacitor, the device starts switching, and increases its current limit in three steps of typically 25ma, 250ma and full current limit (ilim setting). the current-limit transition from the first to the second step occurs after 1ms of operation. full current limit operation is set once the output voltage has reached its regulation limits. in this mode, the active balancing circuit is disabled. nreset input: hardware enable / disable the tps6131x family features a hardware reset pin (nreset). this reset pin allows the device to be disabled by an external controller without requiring an i 2 c write command. under normal operation, the nreset pin should be held high to prevent an unwanted reset. when the nreset is driven low, the i 2 c control interface and all internal control registers are reset to the default states and the part enters shutdown mode. shutdown writing 00 to mode_ctrl[1:0] bits forces the device into shutdown. the shutdown state can only be entered when the voltage regulation (envm = 0) and light modes are both turned off. in the shutdown state: ? the regulator stops switching. ? the high-side pmos disconnects the load from the input. ? the ledx pins are high impedance thus eliminating any dc conduction path. ? the tps6131x device actively discharges the output capacitor when it turns off. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 29 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com serial interface description i 2 c ? is a 2-wire serial interface developed by philips semiconductor, now nxp semiconductors (see i 2 c-bus specification, version 2.1, january 2000). the bus consists of a data line (sda) and a clock line (scl) with pull- up structures. when the bus is idle , both sda and scl lines are pulled high. all the i 2 c compatible devices connect to the i 2 c bus through open drain i/o pins, sda and scl. a master device, usually a microcontroller or a digital signal processor, controls the bus. the master is responsible for generating the scl signal and device addresses. the master also generates specific conditions that indicate the start and stop of data transfer. a slave device receives and/or transmits data on the bus under control of the master device. the tps6131x device works as a slave and supports the following data transfer modes , as defined in the i 2 c- bus specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 mbps). the interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. register contents remain intact as long as supply voltage remains above 2.1v. the data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as f/s- mode in this document. the protocol for high-speed mode is different from f/s-mode, and it is referred to as hs- mode. the tps6131x device supports 7-bit addressing; 10-bit addressing and general call address are not supported. the device 7bit address is defined as ? 011 0011 ? . f/s-mode protocol the master initiates data transfer by generating a start condition. the start condition is when a high-to-low transition occurs on the sda line while scl is high, as shown in figure 50 . all i 2 c-compatible devices should recognize a start condition. figure 50. start and stop conditions the master then generates the scl pulses, and transmits the 7-bit address and the read/write direction bit r/w on the sda line. during all transmissions, the master checks for valid data. a valid data condition requires the sda line to be stable during the entire high period of the clock pulse (see figure 51 ). all devices recognize the address sent by the master and compare it to their internal fixed addresses. only the slave device with a matching address generates an acknowledge (see figure 52 ) by pulling the sda line low during the entire high period of the ninth scl cycle. upon detecting this acknowledge, the master knows that communication link with a slave has been established. figure 51. bit transfer on the serial interface the master generates further scl cycles to either transmit data to the slave (r/w bit 1) or receive data from the slave (r/w bit 0). in either case, the receiver needs to acknowledge the data sent by the transmitter. so an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. 30 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 data line stable; data valid data clk change of data allowed start condition data clk stop condition s p
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 to signal the end of the data transfer, the master generates a stop condition by pulling the sda line from low to high while the scl line is high (see figure 50 ). this releases the bus and stops the communication link with the addressed slave. all i 2 c compatible devices must recognize the stop condition. upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. attempting to read data from register addresses not listed in this section will result in 00h being read out. figure 52. acknowledge on the i 2 c bus figure 53. bus protocol h/s-mode protocol the master generates a start condition followed by a valid serial byte containing hs master code 00001xxx. this transmission is made in f/s-mode at no more than 400 kbps. no device is allowed to acknowledge the hs master code, but all devices must recognize it and switch their internal setting to support 3.4 mbps operation. the master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). after this repeated start condition, the protocol is the same as f/s-mode, except that transmission speeds up to 3.4 mbps are allowed. a stop condition ends the hs-mode and switches all the internal settings of the slave devices to support the f/s-mode. instead of using a stop condition, repeated start conditions should be used to secure the bus in hs-mode. attempting to read data from register addresses not listed in this section will result in 00h being read out. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 31 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com tps6131x i 2 c update sequence the tps6131x requires a start condition, a valid i 2 c address, a register address byte, and a data byte for a single update. after the receipt of each byte, tps6131x device acknowledges by pulling the sda line low during the high period of a single clock pulse. a valid i 2 c address selects the tps6131x. tps6131x performs an update on the falling edge of the acknowledge signal that follows the lsb byte. figure 54. : ? write ? data transfer format in f/s-mode figure 55. ? read ? data transfer format in f/s-mode figure 56. data transfer format in h/s-mode 32 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 slave address r/w a register address a p sr 1 7 1 1 1 1 8 data 8 a/a 1 s hs-master code a 1 1 8 f/s mode hs mode f/s mode data transferred (n x bytes + acknowledge) hs mode continues slave address sr from master to tps6131x from tps6131x to master a = acknowledge a = acknowledge s = start condition sr = repeated start condition p = stop condition slave address r/w a register address a data a p s 1 7 1 1 1 1 1 8 8 0 write sr 1 slave address r/w 7 1 1 read a 1 from master to tps6131x from tps6131x to master a = acknowledge s = start condition sr = repeated start condition p = stop condition slave address r/w a register address a data a p s 1 7 1 1 1 1 1 8 8 0 write from master to tps6131x from tps6131x to master a = acknowledge s = start condition sr = repeated start condition p = stop condition
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 slave address byte msb lsb x x x x x x a1 a0 the slave address byte is the first byte received following the start condition from the master device. register address byte msb lsb 0 0 0 0 00 d2 d1 d0 following the successful acknowledgment of the slave address, the bus master will send a byte to the tps6131x, which will contain the address of the register to be accessed. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 33 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com register descriptions register0 description memory location: 0x00 description reset free dclc13[2:0] dclc2[2:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r/w r/w r/w r/w r/w default value 0 0 0 0 1 0 1 0 bit description reset register reset bit. 0: normal operation. 1: default values are set to all internal registers. dclc13[2:0] video light current control bits (led1/3). 000: 0ma. (1) (2) 001: 25ma 010: 50ma 011: 75ma 100: 100ma 101: 125ma 110: 150ma 111: 175ma dclc2[2:0] video light current control bits (led2). 000: 0ma. (1) (2) 001: 25ma 010: 50ma 011: 75ma 100: 100ma 101: 125ma 110: 150ma, 225ma current level can be activated simultaneously with tx-mask = 1 111: 175ma, 325ma current level can be activated simultaneously with tx-mask = 1 (1) leds are off, v out set according to ov[3:0]. (2) when dclc2[2:0] and dclc13[2:0] are both reset, the device operates in voltage regulation mode. the output voltage is set according to ov[3:0]. 34 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 register1 description memory location: 0x01 description mode_ctrl[1:0] fc2[5:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r/w r/w r/w r/w r/w default value 0 0 0 1 0 0 0 0 bit description mode_ctrl[1:0] mode control bits. 00: device in shutdown mode. 01: device operates in video light mode. 10: device operates in flash mode. 11: device operates as constant voltage source. to avoid device shutdown by video light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 13.0s. writing to register1[7:6] automatically updates register2[7:6]. fc2[5:0] flash current control bits (led2). 000000: 0ma. (1) (2) 000001: 25ma 000010: 50ma 000011: 75ma 000100: 100ma 000101: 125ma 000110: 150ma 000111: 175ma 001000: 200ma 001001: 225ma 001010: 250ma 001011: 275ma 001100: 300ma 001101: 325ma 001110: 350ma 001111: 375ma 010000: 400ma 010001: 425ma 010010: 450ma 010011: 475ma 010100: 500ma 010101: 525ma 010110: 550ma 010111: 575ma 011000: 600ma 011001: 625ma 011010: 650ma 011011: 675ma 011100: 700ma 011101: 725ma 011110: 750ma 011111: 775ma 100000 ... 111111: 800ma (1) leds are off, v out set according to ov[3:0]. (2) when fc13[4:0] and fc2[5:0] are both reset, the device operates in voltage regulation mode. the output voltage is set according to ov[3:0]. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 35 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com register2 description memory location: 0x02 description mode_ctrl[1:0] envm fc13[4:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r/w r/w r/w r/w r/w default value 0 0 0 0 1 0 0 0 bit description mode_ctrl[1:0] mode control bits. 00: device in shutdown mode. 01: device operates in video light mode. 10: device operates in flash mode. 11: device operates as constant voltage source. to avoid device shutdown by video light safety timeout, mode_ctrl[1:0] bits need to be refreshed within less than 13.0s. writing to register2[6:5] automatically updates register1[6:5]. envm enable voltage mode bit. 0: normal operation. 1: forces the device into a constant voltage source. in read mode, the envm bit is automatically updated to reflect the logic state of the envm input pin. fc13[4:0] flash current control bits (led1/3). 00000: 0ma. (1) (2) 00001: 25ma 00010: 50ma 00011: 75ma 00100: 100ma 00101: 125ma 00110: 150ma 00111: 175ma 01000: 200ma 01001: 225ma 01010: 250ma 01011: 275ma 01100: 300ma 01101: 325ma 01110: 350ma 01111: 375ma 10000 ... 11111: 400ma (1) leds are off, v out set according to ov[3:0]. (2) when fc13[4:0] and fc2[5:0] are both reset, the device operates in voltage regulation mode. the output voltage is set according to ov[3:0]. 36 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 register3 description memory location: 0x03 description stim[2:0] hplf selstim (w) stt sft tx-mask to (r) bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r r r/w r/w r/w default value 1 1 0 0 0 0 0 1 bit description stim[2:0] safety timer bits. stim[2:0] range 0 range 1 stim[2:0] range 0 range 1 000 68.2ms 5.3ms 100 204.5ms 26.6ms 001 102.2ms 10.7ms 101 340.8ms 32.0ms 010 136.3ms 16.0ms 110 579.3ms 37.3ms 011 170.4ms 21.3ms 111 852ms 71.5ms hpfl high-power led failure flag. 0: proper led operation. 1: led failed (open or shorted). high-power led failure flag is reset after readout selstim safety timer selection range (write only). 0: safety timer range 0. 1: safety timer range 1. to time-out flag (read only). 0: no time-out event occurred. 1: time-out event occurred. time-out flag is reset at re-start of the safety timer. stt safety timer trigger bit. 0: led safety timer is level sensitive. 1: led safety timer is rising edge sensitive. this bit is only valid for mode_ctrl[1:0] = 10. sft start/flash timer bit. in write mode, this bit initiates a flash strobe sequence. notice that this bit is only active when strb0 input is high. 0: no change in the high-power led current. 1: high-power led current ramps to the flash current level. in read mode, this bit indicates the high-power led status. 0: high-power leds are idle. 1: ongoing high-power led flash strobe. tx-mask flash blanking control bit. in write mode, this bit enables/disables the flash blanking/led current reduction function. 0: flash blanking disabled. 1: led current is reduced to video light level when tx-mask input is high. in read mode, this flag indicates whether or not the flash masking input has been activated. tx-mask flag is reset after readout of the flag. 0: no flash blanking event occurred. 1: tx-mask input triggered. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 37 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com register4 description memory location: 0x04 description pg hotdie[1:0] ilim inc[3:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r r r/w r/w r/w r/w r/w default value 0 0 0 0 0 0 0 0 bit description pg power good bit. in write mode, this bit selects the functionality of the gpio/pg output. 0: pg signal is routed to the gpio port. 1: gpio port value bit is routed to the gpio port. in read mode, this bit indicates the output voltage conditions. 0: the converter is not operating within the voltage regulation limits. 1: the output voltage is within its nominal value. hotdie[1:0] instantaneous die temperature bits. 00: t j < +55 c 01: +55 c < t j < +70 c 10: t j > +70 c 11: thermal shutdown tripped. indicator flag is reset after readout. ilim inductor valley current limit bit. the ilim bit can only be set before the device enters operation (i.e. initial shutdown state). valley current limit ilim bit setting setting TPS61310 tps61311 1250ma 1800ma low 1750ma 2480ma high indc[3:0] indicator light control bits. privacy indicator privacy indicator indc[3:0] indc[3:0] indled channel led1-3 channels (1) 0000 privacy indicator turned off 1000 5% pwm dimming ratio 0001 indled current = 2.6ma (2) 1001 11% pwm dimming ratio 0010 indled current = 5.2ma (2) 1010 17% pwm dimming ratio 0011 indled current = 7.9ma (2) 1011 23% pwm dimming ratio 0100 privacy indicator turned off 1100 30% pwm dimming ratio 0101 indled current = 5.2ma (2) 1101 36% pwm dimming ratio 0110 indled current = 1110 48% pwm dimming ratio 10.4ma (2) 0111 indled current = 15.8ma 1111 67% pwm dimming ratio (2) (1) this mode of operation can only be activated for mode_ctrl[1:0] = 01 & envm = 1. (2) the output node (vout) is internally pulled to ground. 38 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 register5 description memory location: 0x05 description dir (w) selfcal enpsm gpio gpiotype enled3 enled2 enled1 ststrb1 (r) bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r/w r/w r/w r/w r/w default value 0 1 1 0 1 0 1 0 bit description selfcal high-current led forward voltage self-calibration start bit. in write mode, this bit enables/disables the output voltage vs. led forward voltage/current self-calibration procedure. 0: self-calibration disabled. 1: self-calibration enabled. in read mode, this bit returns the status of the self-calibration procedure. 0: self-calibration ongoing 1: self-calibration done notice that this bit is only being reset at the (re-)start of a calibration cycle. enpsm enable / disable power-save mode bit. 0: power-save mode disabled. 1: power-save mode enabled. ststrb1 strb1 input status bit (read only). this bit indicates the logic state on the strb1 state. dir gpio direction bit. 0: gpio configured as input. 1: gpio configured as output. gpio gpio port value. this bit contains the gpio port value. gpiotype gpio port type. 0: gpio is configured as push-pull output. 1: gpio is configured as open-drain output. enled3 enable / disable high-current led3 bit. 0: led3 input is disabled. 1: led3 input is enabled. enled2 enable / disable high-current led2 bit. 0: led2 input is disabled. 1: led2 input is enabled. enled1 enable / disable high-current led1 bit. 0: led1 input is disabled. 1: led1 input is enabled. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 39 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com register6 description memory location: 0x06 description ents ledhot ledwarn ledhdr ov[3:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r r r/w r/w r/w r/w default value 0 0 0 0 1 0 0 1 bit description ents enable / disable led temperature monitoring. 0: led temperature monitoring disabled. 1: led temperature monitoring enabled. ledhot led excessive temperature flag. this bit can be reset by writing a logic level zero. 0: ts input voltage > 0.345v. 1: ts input voltage < 0.345v. ledwarn led temperature warning flag (read only). this flag is reset after readout. 0: ts input voltage > 1.05v. 1: ts input voltage < 1.05v. ledhdr led high-current regulator headroom voltage monitoring bit. this bit returns the headroom voltage status of the led high-current regulators. this value is being updated at the end of a flash strobe, prior to the led current ramp-down phase. 0: low headroom voltage. 1: sufficient headroom voltage. 0v[3:0] output voltage selection bits. in read mode, these bits return the result of the high-current led forward voltage self-calibration procedure. in write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). in applications requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been enabled (mode_ctrl[1:0] = 11 and/or envm bit = 1). ov[3:0] target output voltage 0000 3.825v 0001 3.950v 0010 4.075v 0011 4.200v 0100 4.325v 0101 4.450v 0110 4.575v 0111 4.700v 1000 4.825v 1001 4.950v 1010 5.075v 1011 5.200v 1100 5.325v 1101 5.450v 1110 5.575v 1111 5.700v 40 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 register7 description memory location: 0x07 description enbatmon batdroop[2:0] free revid[2:0] bits d7 d6 d5 d4 d3 d2 d1 d0 memory type r/w r/w r/w r/w r/w r r r default value 0 1 0 0 0 1 1 0 bit description enbatmon enable / disable battery voltage droop monitoring bit 0: battery voltage droop monitoring disabled. 1: battery voltage droop monitoring enabled. batdroop[2:0] battery voltage droop 000: 50mv 001: 75mv 010: 100mv 011: 125mv 100: 150mv 101: 175mv 110: 200mv 111: 225mv revid[2:0] silicon revision id copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 41 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com application information ? inductor selection ? input capacitor ? output capacitor ? ntc selection ? checking loop stability ? led flash current level optimization vs. battery droop ? led forward voltage calibration ? layout considerations ? thermal information ? typical applications inductor selection a boost converter requires two main passive components for storing energy during the conversion. a boost inductor and a storage capacitor at the output are required. the tps6131x device integrates current-limit protection circuitry. the valley current of the pmos rectifier is sensed to limit the maximum current flowing through the synchronous rectifier and the inductor. the valley peak current limit (1250ma/1750ma) is user selectable via the i 2 c interface. in order to optimize solution size the tps6131x device has been designed to operate with inductance values between a minimum of 1.3 h and maximum of 2.9 h. in typical high-current white led applications a 2.2 h inductance is recommended. the highest peak current through the inductor and the power switch depends on the output load, the input and output voltages. the maximum average inductor current and the maximum inductor peak current can be estimated using equation 2 and equation 3 : (2) (3) with f = switching frequency (2mhz) l = inductance value (2.2 h) = estimated efficiency (85%) the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for total circuit efficiency. table 7. list of inductors manufacturer series dimensions ilim settings toko dfe322512 3.2mm x 2.5mm x 1.2mm max height 2480ma (typ.) tdk vlf3014at 2.6mm x 2.8mm x 1.4mm max. height coilcraft lps3015 3.0mm x 3.0mm x 1.5mm max. height 1250ma (typ.) murata lqh2hpn 2.5mm x 2.0mm x 1.2mm max. height toko fdse0312 3.0mm x 3.0mm x 1.2mm max. height 1750ma (typ.) murata lqm32pn 3.2mm x 2.5mm x 1.0mm max. height 42 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 out out in in l(peak) out i v v v d i = + with d = 2 f l (1 d) v - - h out l out in v i i v ?
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 input capacitor for good input-voltage filtering, low esr ceramic capacitors are recommended. a 10 f input capacitor is recommended to improve transient behavior of the regulator and emi behavior of the total power supply circuit. the input capacitor should be placed as close as possible to the input pin of the converter. output capacitor the major parameter necessary to define the output capacitor is the maximum allowed output-voltage ripple of the converter. this ripple is determined by two parameters of the capacitor, the capacitance and the esr. it is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the esr is zero, by using equation 4 : (4) parameter f is the switching frequency and v is the maximum allowed ripple. with a chosen ripple voltage of 10mv, a minimum capacitance of 10 f is needed. the total ripple is larger due to the esr of the output capacitor. this additional component of the ripple can be calculated using equation 5 : (5) the total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the esr of the capacitor. additional ripple is caused by load transients. this means that the output capacitor has to completely supply the load during the charging phase of the inductor. a reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. for the standard current white led application, a minimum of 3 f effective output capacitance is usually required when operating with 2.2 h (typ) inductors. for solution size reasons, this is usually one or more x5r/x7r ceramic capacitors. depending on the material, size and therefore margin to the rated voltage of the used output capacitor, degradation on the effective capacitance can be observed. this loss of capacitance is related to the dc bias voltage applied. it is therefore always recommended to check that the selected capacitors are showing enough effective capacitance under real operating conditions. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 43 product folder links: TPS61310 tps61311 esr out err r i v = d out out in min out i (v v ) c f v v - ? d
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com ntc selection the tps6131x requires a negative thermistor (ntc) for sensing the led temperature. once the temperature monitoring feature is activated, a regulated bias current (c.a. 24 a) is driven out of the ts port to produce a voltage across the thermistor. if the temperature of the ntc-thermistor rises due to the heat dissipated by the led, the voltage on the ts input pin decreases. when this voltage goes below the ? warning threshold ? , the ledwarn bit in register6 is set. this flag is cleared by reading the register. if the voltage on the ts input decreases further and falls below ? hot threshold ? , the ledhot bit in register6 is set and the device goes automatically in shutdown mode to avoid damaging the led. this status is latched until the ledhot flag gets cleared by software. the selection of the ntc-thermistor value strongly depends on the power dissipated by the led and all components surrounding the temperature sensor and on the cooling capabilities of each specific application. with a 220k ? (at 25 c) thermistor, the valid temperature window is set between 60 c to 90 c. the temperature window can be enlarged by adding external resistors to the ts pin application circuit. in order to obtain proper triggering of the ledwarn and ledhot flags in noisy environments, the ts signal may require additional filtering capacitance. figure 57. temperature monitoring characteristic table 8. list of negative thermistor (ntc) manufacturer part number value murata ncp18wm224j03rb 220k ? 44 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 checking loop stability the first step of circuit and stability evaluation is to examine the following signals from a steady-state perspective: ? switching node, sw ? inductor current, i l ? output ripple voltage, v out(ac) these are the basic signals that must be measured when evaluating a switching converter. if the switching waveform shows large duty-cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. this is often a result of improper board layout and/or l-c combination. as a next step in the evaluation of the regulation loop, test the load transient response. vout can be monitored for settling time, overshoot or ringing that helps judge the converter's stability. with no ringing, the loop has usually more than 45 of phase margin. because the damping factor of the circuitry is directly related to several resistive parameters (e.g., mosfet r ds(on) ) that are temperature dependant, the loop stability should be analyzed over the input voltage range, output current range, and temperature range. copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 45 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com led flash current level optimization vs. battery droop in cell phone applications, the camera engine is normally specified over an operating temperature range down to 0 c or ? 10 c. in order to achieve a reliable system operation, the led flash current needs to be rated according to the maximum tolerable battery voltage drop (i.e. highest battery impedance, lowest ambient temperature). to dynamically optimize the led flash current (i.e. light output) vs. battery state-of-charge and temperature, we could consider the following self-adjustment procedure. this algorithm could be embedded into the auto- exposure, auto white-balance or red-eye reduction pre-flash algorithms. figure 58. image capture sequence ? phase 1: pre-flash, battery impedance estimation the battery voltage usually drops by a few hundreds of millivolts during a high-power flash strobe. for short durations, this voltage droop should not be subject to the battery intrinsic capacitance (i.e. relaxation effect) but rather to its cell impedance. based on the state of the tx-mask input, the battery voltage drop (during pre-flash) and the led current level, the base-band processor can compute an estimated cell-impedance value (esr). depending on the ambient temperature, the battery state-of-charge (soc), the flash (capture) duration and the actual status of the various rf interfaces, the base-band processor can determine a safe battery voltage droop (to be tolerated during the forthcoming strobe sequence) as well as a maximum flash current rating. the maximum flash current setting can be estimated by considering nominal leds and approximately 85% power efficiency in the driver. ? phase 2: battery loading monitoring prior to image capture for a reliable system operation, the base-band processor should make sure that no 'parasitic' high-current load suddenly impacts the budgeted battery voltage sag. the most critical timing is referenced as t critical . the interrupt subroutine (running on the base-band processor) should be ready to detect any 'parasitic' battery load event that could occur prior to the image capture (refer to sft bit description). in such a situation, the battery voltage droop budget and the maximum led current settings would need to be revised. 46 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 i (optimum) flash ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ battery voltage measurement base-band processor to compute battery esr t critical flash (capture) (133 ms) pre-flash (3 ms) battery voltage led current flash synchronization (camera isp)
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 figure 59. 900mah, li-ion battery transient response vs. soc and temperature copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 47 product folder links: TPS61310 tps61311
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com led forward voltage calibration high-power leds tend to exhibit a wide forward voltage distribution. the tps6131x device integrates a self- calibration procedure that can be used to determine the actually led forward voltage. the led forward voltage ? in-situ ? characterization can be performed at camera engine production test. this data can help to estimate more precisely the actual led electrical power vs. flash current. this calibration procedure is meant to start at a minimum output voltage, and can be initiated by writing the selfcal bit (preferably with mode_ctrl[1:0] = 00, envm = 0). the calibration procedure monitors the sense voltage across the low-side current regulators (according to enled[3:1] bits setting) and registers the worst case led (i.e. the led featuring the largest forward voltage). the tps6131x device automatically sweeps through its output voltage range and performs a short duration flash strobe for each step (refer to fc13[4:0] and fc2[5:0] bits settings). the sequence is stopped as soon as the device detects that each of the low-side current regulators have enough headroom voltage (i.e. 400mv typ.). the device returns the according output voltage in the register ov[3:0] and sets the selfcal bit. this bit is only being reset at the (re-)start of a calibration cycle. in other words, when selfcal is asserted the output voltage register (ov[3:0]) returns the result of the last calibration sequence. figure 60. led forward voltage calibration principle 48 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 output voltage, v out power good, pg v bat led flash current, i flash ov[3:0] 0000 0001 0010 0011 0100 0101 ~200 m s feedback sense comparator output v led > 400 mv self-calibration, selfcal bit (write) self-calibration, selfcal bit (read) esr x i led ~200 m s feedback sense comparator information x
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 layout considerations as for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. if the layout is not carefully done, the regulator could show stability problems as well as emi problems. therefore, use wide and short traces for the main current path and for the power ground tracks. the input capacitor, output capacitor, and the inductor should be placed as close as possible to the ic. use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. connect these ground nodes at any place close to one of the ground pins of the ic. to lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. this avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. figure 61. suggested layout (top) copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 49 product folder links: TPS61310 tps61311 gnd led1 led2 led3 v in gnd l1 c out c in 1 indled sda strb0ts b2: sclb3: nreset c3: tx_mask d3: strb1 d4: gpio/pg
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com thermal information implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. many system-dependant issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipation limits of a given component. three basic approaches for enhancing thermal performance are listed below: ? improving the power dissipation capability of the pcb design ? improving the thermal coupling of the component to the pcb ? introducing airflow in the system junction-to-ambient thermal resistance is highly dependent on application and board layout. in applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. the maximum junction temperature (t j ) of the tps6131x is 150 c. the maximum power dissipation is especially critical when the device operates in the linear down mode at high led current. for single-pulse power thermal analysis (e.g., flash strobe), the allowable power dissipation for the device is given by figure 62 . these values are derived using the reference design. figure 62. single pulse power capability 50 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200 pulse width - ms p - single pulse constant power dissipation - w dis t = 65c rise j t = 40c rise j no airflow
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 typical applications figure 63. 2x 600ma high power white led solution featuring privacy indicator figure 64. 1200ma high power white led solution featuring ' back-drive ' privacy indicator copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 51 product folder links: TPS61310 tps61311 camera engine flash synchronization rf pa tx active vout avin sw c i sw led 1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl TPS61310 led 2 led 3 d1 2.5 v..5.5 v strb0 strb1 ts gpio/pg indled privacyindicator i 2 c i/f nreset 220k ntc tx-mask hardware reset camera engine flash synchronization rf pa tx active vout avin sw c i sw led 1 c o 10 m f pgnd pgnd agnd l 2.2 m h sda scl TPS61310 led 2 led 3 d1 d2 2.5 v..5.5 v strb0 strb1 ts gpio/pg indled privacyindicator i 2 c i/f nreset 220k ntc tx-mask hardware reset
TPS61310 , tps61311 slvs978c ? march 2010 ? revised november 2012 www.ti.com package summary chip scale package chip scale package (bottom view) (top view) note: " abc " is a place holder for the actual package marking. (see table 1 ) chip scale package dimensions the tps6131x device is available in a 20-bump chip scale package (yff, nanofree ? ). the package dimensions are given as: ? d = 2170 30 m ? e = 1928 30 m 52 submit documentation feedback copyright ? 2010 ? 2012, texas instruments incorporated product folder links: TPS61310 tps61311 a1b1 d e a2b2 a3b3 a4b4 c2 c1 c3 c4 e2 e1 e3 e4 d2 d1 d3 d4 abc a1
TPS61310 , tps61311 www.ti.com slvs978c ? march 2010 ? revised november 2012 revision history changes from revision a (october 2010) to revision b page ? changed v uvlo to max value from 2.35v to 2.4v. ............................................................................................................... 3 ? added t j = +25 c, to v do test conditions, max value from 200mv to 250mv. .................................................................... 4 ? updated sft bit description. .............................................................................................................................................. 37 ? updated led forward voltage calibration description. ........................................................................................................ 48 changes from revision b (september 2011) to revision c page ? added revision letter c to literature number ......................................................................................................................... 1 ? added tps61311 to ordering table ...................................................................................................................................... 2 ? added current limit setting for tps61311 ........................................................................................................................ 28 ? added current limit setting for tps61311 in register map .................................................................................................. 38 copyright ? 2010 ? 2012, texas instruments incorporated submit documentation feedback 53 product folder links: TPS61310 tps61311
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS61310yffr dsbga yff 20 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 q1 TPS61310yfft dsbga yff 20 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 q1 tps61311yffr dsbga yff 20 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 q1 tps61311yfft dsbga yff 20 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 q1 package materials information www.ti.com 26-jan-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS61310yffr dsbga yff 20 3000 210.0 185.0 35.0 TPS61310yfft dsbga yff 20 250 210.0 185.0 35.0 tps61311yffr dsbga yff 20 3000 210.0 185.0 35.0 tps61311yfft dsbga yff 20 250 210.0 185.0 35.0 package materials information www.ti.com 26-jan-2013 pack materials-page 2

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